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品牌：Intel
类别：芯片组
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品牌：Intel
类别：芯片组
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品牌：Intel
类别：芯片组
-
品牌：Intel
类别：芯片组
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品牌：Intel
类别：芯片组
| 参数 | 数值 |
|---|---|
| Product name | Intel® 5100 Memory Controller |
| Code Name | Formerly San Clemente |
| Datasheet | Download Datasheet |
| Dual Independent Display | No |
| ECC Memory | True |
| FSB Speed | 667MHz, 1066MHz, 1333MHz |
| Graphics Output | None |
| Integrated Graphics | No |
| Launch Date | Q4'07 |
| License Required | No |
| Low Halogen Available | See MDDS |
| Max Memory | 48 GB |
| Max TDP | 25.7 Watts |
| Number of Memory Channels | 2 |
| Package Size | 38.5mm x 42.5mm |
| TCase | 105°C |
这些基于四核、双核及单核英特尔® 至强® 处理器的平台采用 45 纳米和 65 纳米制程技术；拥有出色的性能、能效和极长的生命周期支持，是进行密集计算的存储与通信应用的理想选择。
- 英特尔® 虚拟化技术： 允许硬件平台作为多个虚拟平台。
- Intel® 64 架构： 支持 64 位指令。
- 多核选项： 提高应对多线程应用的性能
- 英特尔® SSE4 指令： 47 条新指令用以提高应对媒体与高性能计算应用的性能。
交互式结构图
应用注释
| 序号 | 描述 | |
|---|---|---|
| 1 | White Paper: Choosing the Right Storage Solution for Your Embedded Application | White Paper: Choosing the Right Storage Solution for Your Embedded Application |
| 2 | White Paper: How to Properly Measure Cache Latency, Memory Latency, and CPU to Memory Bandwidth on I | White Paper: How to Properly Measure Cache Latency, Memory Latency, and CPU to Memory Bandwidth on Intel® Architecture |
| 3 | White Paper: Extending the World’s Most Popular Processor Architecture | White Paper: Extending the World’s Most Popular Processor Architecture |
| 4 | White Paper: Embedded Intel® Architecture and High Speed Digital Design Principles | White Paper: Embedded Intel® Architecture and High Speed Digital Design Principles |
| 5 | White Paper: Designing Systems without a Suspend Supply | White Paper: Designing Systems without a Suspend Supply |
| 6 | White Paper: DDR Signal Integrity (SI) Simulation Process for Intel® Architecture Platforms | White Paper: DDR Signal Integrity (SI) Simulation Process for Intel® Architecture Platforms |
| 7 | White Paper: Consolidating Communications and Networking Workloads onto One Architecture | White Paper: Consolidating Communications and Networking Workloads onto One Architecture |
| 8 | White Paper: Interfacing I²C Devices to Intel's SMBus Controller | White Paper: Interfacing I²C Devices to Intel's SMBus Controller |
| 9 | White Paper: Asymmetric Multi-Processing, Embedded and Communication MC Usage Model | White Paper: Asymmetric Multi-Processing, Embedded and Communication MC Usage Model |
| 10 | White Paper: Accessing PCI Express* Registers When Using Intel® Chipsets | White Paper: Accessing PCI Express* Registers When Using Intel® Chipsets |
| 11 | White Paper: Reducing Interrupt Latency in Embedded Systems through Message Signaled Interrupts | White Paper: Reducing Interrupt Latency in Embedded Systems through Message Signaled Interrupts |
| 12 | White Paper: What Does It Mean to Be I/O Bound? | White Paper: What Does It Mean to Be I/O Bound? |
| 13 | White Paper: Upgrading to Multi-Core Ecosystem Keeps Car Simulator Running in the Fast Lane | White Paper: Upgrading to Multi-Core Ecosystem Keeps Car Simulator Running in the Fast Lane |
| 14 | White Paper: Thermal Guidance for AdvancedTCA Designs | White Paper: Thermal Guidance for AdvancedTCA Designs |
| 15 | White Paper: Signal Integrity Pitfalls When You Deviate from Intel Design Guidelines | White Paper: Signal Integrity Pitfalls When You Deviate from Intel Design Guidelines |
| 16 | White Paper: Seven Tips to Get Started on Embedded Multi-Core | White Paper: Seven Tips to Get Started on Embedded Multi-Core |
| 17 | White Paper: Programming Models for Packet Processing Applications on Multi-Core Intel® Architecture | White Paper: Programming Models for Packet Processing Applications on Multi-Core Intel® Architecture Systems |
| 18 | White Paper: Platform-Level error Handling Strategies for Intel® Systems | White Paper: Platform-Level error Handling Strategies for Intel® Systems |
| 19 | White Paper: PCB Stackup Overview for Intel® Architecture Platforms—Layout and Signal Integrity Cons | White Paper: PCB Stackup Overview for Intel® Architecture Platforms—Layout and Signal Integrity Considerations |
| 20 | White Paper: Optimizing Embedded System Performance—Impact of Data Prefetching on a Medical Imaging | White Paper: Optimizing Embedded System Performance—Impact of Data Prefetching on a Medical Imaging Application |
| 21 | White Paper: JTAG 101 | White Paper: JTAG 101 |
| 22 | White Paper: Introducing the 45nm Next-Generation Intel® Core Microarchitecture | White Paper: Introducing the 45nm Next-Generation Intel® Core Microarchitecture |
| 23 | Case Study: Migrating the Ericsson* Operations Support System: RISC or Intel® based Servers | Case Study: Migrating the Ericsson* Operations Support System: RISC or Intel® based Servers |
| 24 | Application Note: Designing Embedded Systems for Testability | Application Note: Designing Embedded Systems for Testability |
| 25 | Application Note: AP-485 Intel® Processor Identification and CPUID Instruction | Application Note: AP-485 Intel® Processor Identification and CPUID Instruction |
| 26 | Application Note: Alcatel-Lucent Converged IP Messaging Solution | Application Note: Alcatel-Lucent Converged IP Messaging Solution |
性能指标评测
| 序号 | 描述 | |
|---|---|---|
| 1 | White Paper: How to Properly Measure Cache Latency, Memory Latency, and CPU to Memory Bandwidth on I | White Paper: How to Properly Measure Cache Latency, Memory Latency, and CPU to Memory Bandwidth on Intel® Architecture |
| 2 | White Paper: Hardware Level I/O Benchmarking of PCI Express on Intel® Platforms | White Paper: Hardware Level I/O Benchmarking of PCI Express on Intel® Platforms |
| 3 | White Paper: Layer 3 Forwarding and IPSec Measurement and Optimization | White Paper: Layer 3 Forwarding and IPSec Measurement and Optimization |
散热和机械
| 序号 | 描述 | |
|---|---|---|
| 1 | Thermal & Mechanical Design Guidelines: Quad-Core Intel® Xeon® Processor 5400 Series | Thermal & Mechanical Design Guidelines: Quad-Core Intel® Xeon® Processor 5400 Series |
| 2 | Thermal & Mechanical Design Guidelines: Intel® Xeon® Processor L5408 Series in Embedded Applications | Thermal & Mechanical Design Guidelines: Intel® Xeon® Processor L5408 Series in Embedded Applications |
| 3 | Thermal & Mechanical Design Guidelines: Intel® Xeon® Processor 5200 Series in Embedded Applications | Thermal & Mechanical Design Guidelines: Intel® Xeon® Processor 5200 Series in Embedded Applications |
| 4 | Thermal & Mechanical Design Guidelines: Intel® Xeon® Processor 5200 Series | Thermal & Mechanical Design Guidelines: Intel® Xeon® Processor 5200 Series |
| 5 | Thermal & Mechanical Design Guide: Intel® 5100 Memory Controller Hub Chipset | Thermal & Mechanical Design Guide: Intel® 5100 Memory Controller Hub Chipset |
| 6 | White Paper: Thermal Design Considerations for Embedded Applications | White Paper: Thermal Design Considerations for Embedded Applications |
| 7 | Power Profiling for Embedded Applications | Power Profiling for Embedded Applications |
开发主板和套件
| 序号 | 描述 | |
|---|---|---|
| 1 | 开发套件: 四核和双核英特尔®至强®处理器5000系列和 英特尔®5100内存控制器芯片组开发套件 | 开发套件: 四核和双核英特尔®至强®处理器5000系列和 英特尔®5100内存控制器芯片组开发套件 |
| 2 | Development Kit User Guide: Intel® Xeon® Processor 5000 Sequence and Intel® 5100 Memory Controller H | Development Kit User Guide: Intel® Xeon® Processor 5000 Sequence and Intel® 5100 Memory Controller Hub Chipset |
产品简介
| 序号 | 描述 | |
|---|---|---|
| 1 | 产品简介： 45 纳米英特尔® 至强® 处理器 5400/5200 系列 | 产品简介： 45 纳米英特尔® 至强® 处理器 5400/5200 系列 |
| 2 | Development Kit User Guide: Intel® Xeon® Processor 5000 Sequence and Intel® 5100 Memory Controller H | Development Kit User Guide: Intel® Xeon® Processor 5000 Sequence and Intel® 5100 Memory Controller Hub Chipset |
| 3 | Product Brief: Intel® 5100 Memory Controller Hub Chipset for Embedded Computing | Product Brief: Intel® 5100 Memory Controller Hub Chipset for Embedded Computing |
| 4 | Product Brief: Intel® 82576 Gigabit Ethernet Controller | Product Brief: Intel® 82576 Gigabit Ethernet Controller |
| 5 | Product Brief: Intel® 82599 10 Gigabit Ethernet Controller (Network Connectivity) | Product Brief: Intel® 82599 10 Gigabit Ethernet Controller (Network Connectivity) |
数据表和规格更新
| 序号 | 描述 | |
|---|---|---|
| 1 | Specification Update: Quad-Core Intel® Xeon® Processor 5400 Series | Specification Update: Quad-Core Intel® Xeon® Processor 5400 Series |
| 2 | Datasheet: Intel® 82599 10 Gigabit Ethernet (GbE) Controller | Datasheet: Intel® 82599 10 Gigabit Ethernet (GbE) Controller |
| 3 | DB400/800 Differential Clock Buffer Specification | DB400/800 Differential Clock Buffer Specification |
| 4 | Datasheet: Quad-Core Intel® Xeon® Processor 5400 Series | Datasheet: Quad-Core Intel® Xeon® Processor 5400 Series |
| 5 | Datasheet: Intel® I/O Controller Hub 9 (ICH9) Family | Datasheet: Intel® I/O Controller Hub 9 (ICH9) Family |
| 6 | Datasheet: Intel® 82576 Gigabit Ethernet (GbE) Controller | Datasheet: Intel® 82576 Gigabit Ethernet (GbE) Controller |
| 7 | Datasheet: Intel® 5100 Memory Controller Hub | Datasheet: Intel® 5100 Memory Controller Hub |
| 8 | Specification Update: Intel® 5100 Memory Controller Hub (MCH) Chipset Specification Update | Specification Update: Intel® 5100 Memory Controller Hub (MCH) Chipset Specification Update |
| 9 | Specification Update: Intel® 82576 Gigabit Ethernet Controller | Specification Update: Intel® 82576 Gigabit Ethernet Controller |
| 10 | Specification Update: Intel® Xeon® Processor 5200 Series | Specification Update: Intel® Xeon® Processor 5200 Series |
设计计算器和清单
| 序号 | 描述 | |
|---|---|---|
| 1 | Design Guide: Voltage Regulator Module (VRM) 9.0 DC-DC Converter | Design Guide: Voltage Regulator Module (VRM) 9.0 DC-DC Converter |
| 2 | Design Guide: LGA771 Socket | Design Guide: LGA771 Socket |
| 3 | Design Guide: ITP700 Debug Port | Design Guide: ITP700 Debug Port |
| 4 | Design Guide: 603-Pin Socket | Design Guide: 603-Pin Socket |
| 5 | Design Guide: Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0 | Design Guide: Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0 |
| 6 | Design Guide: Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1 | Design Guide: Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1 |
以太网控制器
| 序号 | 描述 | |
|---|---|---|
| 1 | Datasheet: Intel® 82599 10 Gigabit Ethernet (GbE) Controller | Datasheet: Intel® 82599 10 Gigabit Ethernet (GbE) Controller |
| 2 | Datasheet: Intel® 82576 Gigabit Ethernet (GbE) Controller | Datasheet: Intel® 82576 Gigabit Ethernet (GbE) Controller |
| 3 | Product Brief: Intel® 82576 Gigabit Ethernet Controller | Product Brief: Intel® 82576 Gigabit Ethernet Controller |
| 4 | Product Brief: Intel® 82599 10 Gigabit Ethernet Controller (Network Connectivity) | Product Brief: Intel® 82599 10 Gigabit Ethernet Controller (Network Connectivity) |
| 5 | Specification Update: Intel® 82576 Gigabit Ethernet Controller | Specification Update: Intel® 82576 Gigabit Ethernet Controller |
模拟模型
| 序号 | 描述 | |
|---|---|---|
| 1 | Boundary Scan Description Language (BSDL): Intel® Xeon® Processor 5200 Series | Boundary Scan Description Language (BSDL): Intel® Xeon® Processor 5200 Series |
示意图和规划文件
| 序号 | 描述 | |
|---|---|---|
| 1 | Development Kit User Guide: Intel® Xeon® Processor 5000 Sequence and Intel® 5100 Memory Controller H | Development Kit User Guide: Intel® Xeon® Processor 5000 Sequence and Intel® 5100 Memory Controller Hub Chipset |
平台概述
| 序号 | 描述 | |
|---|---|---|
| 1 | Intel® 5100 MCH Chipset Launch Presentation | Intel® 5100 MCH Chipset Launch Presentation |
