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The Cadence® Virtuoso® UltraSim Full-Chip Simulator is a high-performance transistor-level FastSPICE circuit simulator for verifying large custom, analog/mixed-signal, RF, memory and SoC designs. It uses true hierarchical simulation with patented isomorphic and adaptive partitioning algorithms to provide the capacity, accuracy, and speed required for design and verification, regardless of design type or stage in the design cycle.

Features/Benefits

• Accelerates pre-and post-layout simulation for a wide range of applications from blocks to full-chip SoCs
  • Basic and advanced circuit diagnostics
  • Advanced parasitic reduction algorithm
  • Advanced algorithm for custom digital verification
• Offers design verification flexibility through various modes
• Delivers silicon-accurate simulation
• Has the flexibility to switch between environments for different design stages via integration with Virtuoso Analog Design Environment
• Delivers high analog capacity and simulation speed for AMS simulation solutions for block authoring and final verification