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Cadence® VoltageStorm Power Verification automates the analysis and optimization of de-coupling capacitance size and location, and it reduces dynamic IR drop on the most complex, low-power designs. VoltageStorm Power Verification provides accurate power consumption data (static and dynamic power calculation, including state-dependent leakage), which is an increasing concern for nanometer-scale designs.
Features/Benefits
- Automates the management of IR drop, from planning through signoff
- Eliminates over-design
- Decreases the risk of IR drop-related failures and power-rail electromigration failures early in the design process
Conference Paper
| 序号 | 描述 | |
|---|---|---|
| 1 | An Effective EM/IR-Drop Flow with UltraSim and VoltageStorm/ ElectronStorm Options | An Effective EM/IR-Drop Flow with UltraSim and VoltageStorm/ ElectronStorm Options |
| 2 | Dynamic IR-Drop Analysis with VoltageStorm DG Using Different Power Grid Views for Cell Modeling | Dynamic IR-Drop Analysis with VoltageStorm DG Using Different Power Grid Views for Cell Modeling |
| 3 | Low-Power Design of DLX Processor Core using Encounter Platform | Low-Power Design of DLX Processor Core using Encounter Platform |
| 4 | Real Design Challenges of Low-Power Physical Implementation | Real Design Challenges of Low-Power Physical Implementation |
| 5 | UltraSim Netlist-Based Memory EMIR Flow | UltraSim Netlist-Based Memory EMIR Flow |
Demo
| 序号 | 描述 | |
|---|---|---|
| 1 | Cadence Low-Power Solution Demo | Cadence Low-Power Solution Demo |
eBook
| 序号 | 描述 | |
|---|---|---|
| 1 | Practical Guide to Low-Power Design - User Experience with CPF | Practical Guide to Low-Power Design - User Experience with CPF |
Datasheet
| 序号 | 描述 | |
|---|---|---|
| 1 | VoltageStorm Power and Power Rail Verification Datasheet | VoltageStorm Power and Power Rail Verification Datasheet |
