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Cadence® Incisive® Design Team Simulator provides testbench creation, reuse, and analysis capabilities to verify designs from the system level, through RTL, to the gate level. The environment supports a coverage-driven methodology from verification planning to closure. Incisive Design Team Simulator’s native-compiled architecture speeds the simultaneous simulation of behavioral, transaction (TLM), RTL, and gate-level models, eliminating the performance degradation in traditional co-simulation. It also supports industry-standard verification languages and is compatible with the Open Verification Methodology (OVM, so engineers can quickly and easily integrate Incisive Design Team Simulator with established verification flows.

Features/Benefits

• Supports testbench generation, analysis, and reuse
• Offers comprehensive coverage capabilities including code, functional, and transactional
• Provides HDL analysis capabilities
• Drives and guides verification with an automatically backannotated and executable verification plan
• Automates the transfer of coverage data to verification management products
• Supports SystemC®, SystemVerilog, Verilog®, VHDL , PSL, and SVA