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When digital simulation became common-place in the 1980s, flows were simple: RTL, then gate, then implement. In the intervening years, simulation has matured into verification and become the critical means to enable productivity, predictability, and quality in modern, complex FPGAs, ASICs, and custom designs. As part of that maturation, new means for generating metrics to measure the progress against the verification plan, new abstractions for both digital and analog simulation moving verification earlier in the process, and new means for speeding convergence have emerged. IES continues to lead these changes in the verification process by adding new technology to support each of these new niches that have emerged making IES the most used engine in the industry.

Today, the Cadence^® Incisive^® Enterprise Simulator fuels testbench automation, reuse, and analysis to verify designs from the system level, through RTL, to the gate level. It supports the metric-driven approach implemented by the Incisive Enterprise Manager. Its native-compiled architecture speeds the simultaneous simulation of transaction-level, behavioral, low-power, RTL, and gate-level models, eliminating the performance degradation often seen in other simulation approaches.

Incisive Enterprise Simulator also supports all IEEE-standard languages, the (OVM), the emerging Accellera Universal Verification Methodology (UVM), and the e Reuse Methodology (eRM), so engineers can quickly and easily integrate it with established verification flows. Verification engineers can extend the functionality of Enterprise Simulator with , which provide a high-throughput channel between the testbench and the device under test (DUT), and enable automated metric driven verification of embedded software exactly as if it were another part of the DUT.

Benefits

• Fuels testbench automation, analysis, and reuse for increased productivity
• Ensures verification quality by tracking industry-standard coverage metrics, including functional, transactional, low-power, and HDL code, plus automatic data and assertion checking
• Drives and guides verification with an automatically backannotated and executable verification plan
• Creates reusable sequences and multi-channel virtual sequences on top of a multi-language verification environment
• Configures existing Universal Verification Components (UVCs) or quickly constructs all-new UVCs
• Enables advanced debug using SimVision for transaction-level models, SystemVerilog/e class libraries, transient mixed-signal, low-power, and traditional waveform analysis
• Supports e, Open Verification Library (OVL), OVM class library, emerging UVM class library, SystemC®, SystemC Verification Library, SystemVerilog, Verilog®, VHDL, PSL, SVA, and CPF
• Delivers the highest possible performance for mixed-language, mixed-signal, and low-power designs, across multiple levels of abstraction, including the ability to “hot swap” the RTL simulation in/out of the Palladium XP series of accelerators/emulators