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The Cadence® Incisive® Plan-to-Closure Methodology reduces risk in the verification of full chips and SoCs by providing a system of best practices and procedures that streamline the process and ensure system-level quality. It spans the full spectrum of verification needs, from automated executable plan creation, to assertion-based verification, to testbench automation and reuse, to full system verification.

The Plan-to-Closure Methodology steers verification based on optimized methods tested on real projects. It includes the following components:

• “Golden” executable examples that serve as learning aids and working templates
• Knowledge System, a web-based portal technology that includes documented best practices and reuse guidelines
• Libraries (code building blocks and utilities) that automate the process and eliminate many redundant verification coding tasks

Since it is an incrementally adoptable, standalone methodology, both RTL design and verification teams and multi-specialist enterprise teams benefit from the Plan-to-Closure Methodology. It supports block- and chip-level design and verification, but also covers SoC development and system-level verification (via the System Verification Methodology, SystemC® language support, transaction-level modeling, HW/SW co-verification, transaction-based acceleration, and in-circuit emulation).

Benefits

• Ensures verification quality with a comprehensive plan- and metric-driven approach
• Supports assertion-based verification, allowing engineers to start verification earlier by using and leveraging assertions at any level (formal analysis to simulation to acceleration/emulation)
• Boosts productivity through reuse of plug-and-play Verification IP, executable templates, and libraries of code building blocks
• Supports mixed-language IP reuse with the Universal Reuse Methodology, which handles e-only, SystemVerilog-only, or mixed-language verification components
• Automates and unifies planning and management, assertion-based verification, testbench automation and reuse, and full-system verification into one methodology
• Optimizes wireless and consumer SoC design via integration with the Cadence SoC Functional Verification Kit
• Supports incremental adoption according to user needs