Cadence® Virtuoso® AMS Designer is a mixed-signal simulation solution for the design and verification of analog, RF, memory, and mixed-signal SoCs. It is integrated with the Virtuoso full-custom environment for mixed-signal design and verification. It is also integrated with the Cadence Incisive® functional verification platform for mixed-signal verification within the digital verification environment.
Features/Benefits
- Ensures design quality with proven Virtuoso analog and Incisive digital simulation technologies
- Supports both analog design flow use model in Virtuoso Analog Design Environment as well as digital verification use model in Incisive Environment
- Supports top-down methodology to quickly detect design failures early in the design cycle to make sure the design is ready for tape-out, right on time
- Accelerates simulation with mixed-signal hardware description language support
- Accelerates simulation of RF circuits at full SPICE accuracy by combining envelope analysis of RF transceivers with digital baseband simulation
Conference Paper
| 序号 | 描述 | |
|---|---|---|
| 1 | Full-Chip Mixed-Signal Verification Using High Precision Digital-Analog Interface Element | Full-Chip Mixed-Signal Verification Using High Precision Digital-Analog Interface Element |
| 2 | Speed Up RF Mixed-Signal Simulation Using Novel Hierarchical Fast Envelope Simulation | Speed Up RF Mixed-Signal Simulation Using Novel Hierarchical Fast Envelope Simulation |
| 3 | Mixed-Signal Assertion Based Verification | Mixed-Signal Assertion Based Verification |
| 4 | Mixed Signal Verification Methodology Using AMS-Ultra | Mixed Signal Verification Methodology Using AMS-Ultra |
| 5 | Full-Chip Verification Flow with Third-Party IP Using AMS Methodology | Full-Chip Verification Flow with Third-Party IP Using AMS Methodology |
| 6 | A Top Down Design Methodology for Mixed-signal Integrated Circuits using the VppSim Simulator | A Top Down Design Methodology for Mixed-signal Integrated Circuits using the VppSim Simulator |
| 7 | Co-simulation: Virtuoso AMS Simulators and Simulink (Mathworks) on Real Designs | Co-simulation: Virtuoso AMS Simulators and Simulink (Mathworks) on Real Designs |
| 8 | AMS Designer Migration, Usability, and Performance Improvements | AMS Designer Migration, Usability, and Performance Improvements |
Datasheet
| 序号 | 描述 | |
|---|---|---|
| 1 | Virtuoso Multi-Mode Simulation Datasheet | Virtuoso Multi-Mode Simulation Datasheet |
| 2 | Assura Design Rule Checker Datasheet | Assura Design Rule Checker Datasheet |
Demo
| 序号 | 描述 | |
|---|---|---|
| 1 | Virtuoso Custom Design Demo: Virtuoso Constraint Flow (IC 6.1 release) | Virtuoso Custom Design Demo: Virtuoso Constraint Flow (IC 6.1 release) |
| 2 | Virtuoso Custom Design Demo: Solving D/MS Design Challenges with Virtuoso AMS Designer | Virtuoso Custom Design Demo: Solving D/MS Design Challenges with Virtuoso AMS Designer |
Cadence Article
| 序号 | 描述 | |
|---|---|---|
| 1 | Getting Plastered Article | Getting Plastered Article |
Brochure
| 序号 | 描述 | |
|---|---|---|
| 1 | Cadence Virtuoso Custom Design Platform Brochure | Cadence Virtuoso Custom Design Platform Brochure |
Success Story
| 序号 | 描述 | |
|---|---|---|
| 1 | Cadence and TowerJazz Success Story | Cadence and TowerJazz Success Story |
| 2 | Cadence and Texas Instruments Success Story | Cadence and Texas Instruments Success Story |
| 3 | Cadence and LSI Corporation Success Story | Cadence and LSI Corporation Success Story |
White Paper
| 序号 | 描述 | |
|---|---|---|
| 1 | Accelerating Analog Simulation with Full Spice Accuracy White Paper | Accelerating Analog Simulation with Full Spice Accuracy White Paper |
