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By enabling placement-aware pin assignment synthesis—which is FPGA device rules accurate—the Allegro FPGA System Planner offers a unique set of capabilities for FPGA-PCB co-design. It provides a floorplan view to place components in the FPGA system and allows users to specify connectivity between components within the FPGA sub-system at a higher level through interface definitions. With its placement aware-pin assignment synthesis, the Allegro FPGA System Planner enables users to explore their FPGA-based architecture and to create an optimum correct-by-construction pin assignment for either production or prototype designs that use FPGAs.

Features/Benefits

• Scalable FPGA-PCB co-design solution from OrCAD Capture to Allegro GXL
• Shortens time for optimum initial pin assignment, accelerating PCB design schedules
• Accelerates integration of FPGAs with Cadence PCB design creation environments
• Eliminates unnecessary, frustrating design iterations during the PCB layout process
• Eliminates unnecessary physical prototype iterations due to FPGA pin assignment errors
• Reduces PCB layer count through placement-aware pin assignment and optimization
• Enables interface-based connectivity definition for the FPGA system
• Enables placement-aware pin assignment synthesis that is FPGA-DRC accurate
• Allows architectural exploration for FPGA system
• Speeds ASIC prototyping using FPGAs