Already proven in thousands of tapeouts, Encounter Conformal EC is the industry’s most widely supported independent equivalence checking product. It is production-proven on more physical design closure products, advanced synthesis software, ASIC libraries, and IP cores than any other formal verification technology.
Benefits
- Exhaustively verifies multi-million–gate ASICs and FPGAs several times faster than traditional gate-level simulation
- Decreases the risk of missing critical bugs with independent verification technology
- Enables faster, more accurate bug detection and correction throughout the entire design flow
- Extends equivalence checking capability to complex datapaths and closes the RTL-to-layout verification gap (XL configuration)
- Ensures RTL models perform the same functions as the corresponding transistor circuits implemented on silicon (GXL configuration)
Success Story
| 序号 | 描述 | |
|---|---|---|
| 1 | Cadence and NetEffect Success Story | Cadence and NetEffect Success Story |
Demo
| 序号 | 描述 | |
|---|---|---|
| 1 | Cadence Encounter Digital IC Design Demo: Necessary and Absolute Signoff Analysis for 65/45nm Design | Cadence Encounter Digital IC Design Demo: Necessary and Absolute Signoff Analysis for 65/45nm Design |
Brochure
| 序号 | 描述 | |
|---|---|---|
| 1 | Cadence Encounter Digital IC Design Platform Brochure | Cadence Encounter Digital IC Design Platform Brochure |
Datasheet
| 序号 | 描述 | |
|---|---|---|
| 1 | Common Platform Datasheet for Cadence 65nm Low-Power Reference Flow | Common Platform Datasheet for Cadence 65nm Low-Power Reference Flow |
| 2 | Encounter Conformal Equivalence Checker Datasheet | Encounter Conformal Equivalence Checker Datasheet |
Conference Paper
| 序号 | 描述 | |
|---|---|---|
| 1 | Functional ECO with Conformal Technology | Functional ECO with Conformal Technology |
| 2 | Low-Power Verification Flow to Ease the Pain of Implementing MTCMOS-based MSMV Wireless Designs | Low-Power Verification Flow to Ease the Pain of Implementing MTCMOS-based MSMV Wireless Designs |
| 3 | Static Verification for Design Reuse and Quality | Static Verification for Design Reuse and Quality |
