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The Cadence® Palladium® series delivers high system throughput, verification automation, and advanced debug to perform plan- and metric-driven system-level hardware/software co-verification. Capable of handling chip designs of up to 256 million gates, it also enables software to be developed and verified on a real hardware implementation using live data.

The Palladium series leverages advanced RTL and ESL verification automation features, such as assertion-based acceleration and transaction-based acceleration. It also uses “real-world” stimuli provided by external equipment. The Palladium series emulates HW/SW designs at up to MHz speeds— months before silicon tapeout—reducing the risk in committing to final silicon.

The Palladium series is available in I, II, and III configurations.

Features/Benefits

• Reduces time to results with high throughput (up to 1,000,000X faster than RTL simulation)
• Eases adoption with fast bring-up time from simulation to acceleration and emulation
• Speeds time to closure via advanced interactive runtime debug with dynamic probes and events, FullVision and Infinite Trace
• Teams with “real-world” external test equipment and systems via plug-n-play SpeedBridge® adapters for standard bus protocols
• Leverages Incisive Enterprise Manager to manage verification system-wide
• Supports industry standard languages:
  - Testbench development: Verilog®, SystemVerilog, C, C++, SystemC® Verification Library, and e
  - Assertion-based acceleration: OVL, PSL, SVA, and the Incisive Assertion Library
  - Transaction-based acceleration: SystemC, C, C++, and e models
  - Assertion-based verification IP: AHB, AXI, Gigabit Ethernet (GMII), USB 2.0